1. Field of the Invention
The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a FinFET device and a method for making the same.
2. Related Art
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs), is the next step in the evolution of CMOS devices. FinFETs are non-planar semiconductor devices which include at least one semiconductor fin protruding from a surface of a substrate. A gate dielectric can be formed in direct physical contact with each vertical sidewall of the at least one semiconductor fin and, optionally, in direct physical contact with a topmost surface of the semiconductor fin. A gate conductor can be formed on the gate dielectric and straddling a portion of the at least one semiconductor fin. FinFETs can increase the on-current per unit area relative to planar field effect transistors.
Referring first to FIG. 1, there is illustrated a device, which includes from top to bottom, a bulk silicon substrate 13, an insulator layer 12 and a handle substrate 10. The device shown in FIG. 1 can be used to make a FinFET device or equivalent structure. As shown with reference to FIG. 2, in preparation for producing a FinFET device, an insulator layer 14 is deposited on top of the bulk silicon substrate 13. This can be done using various techniques known in the art, such as by thermal oxidation or PECVD oxide deposition. Accordingly, FIG. 3 illustrates the device of FIG. 2 after it has undergone one of the various know techniques known in the art, such as an SIT process or direct patterning. The various steps and processes necessary for fin formation are known, and are omitted herein.
FIG. 3, from top to bottom, includes remnants of the insulator layer 14, hereinafter referred to as the insulator material layer 15, a plurality of fins 18 dispersed on top of the insulator layer 12, which in turn is over the handle substrate 10. Collectively the handle substrate 10 and the buried insulator layer 12 may be referred to herein as a semiconductor-on-insulator (SOI) substrate. The handle substrate 10 provides mechanical support for the buried insulator layer 12 and any other layer or material that can be stacked thereupon.
In some embodiments of the present application, the handle substrate 10 can be a semiconductor material, where the term “semiconductor” as used herein in connection with the semiconductor material of the handle substrate 10 denotes any semiconducting material including, for example, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other like III/V compound semiconductors. Multilayers of these semiconductor materials can also be used. In one embodiment, the handle substrate 10 is silicon. In some embodiments, as for example, those involving the stacking of multiple layers, the handle substrate 10 is a non-semiconductor material including, for example, a dielectric material and/or a conductive material.
In some embodiments, the handle substrate 10 can have the crystal orientation of {100}, {110}, or {111}. Other crystallographic orientations besides those specifically mentioned can also be used in the present application. The handle substrate 10 can be a single crystalline semiconductor material, a polycrystalline material, or an amorphous material. In some embodiments, the handle substrate 10 can be processed to include semiconductor regions having different crystal orientations.
The buried insulator layer 12 can be a crystalline or non-crystalline oxide or nitride. In one embodiment, the buried insulator layer 12 is an oxide such as, for example, silicon dioxide. The buried insulator layer 12 can be continuous or it may be discontinuous. When a discontinuous buried insulator region is present, the insulator region can exist as an isolated island that is surrounded by semiconductor material.
The insulator layer 14, and by extension the insulator material layer 15, (which as stated is the remnant of insulator layer 14), is located over the plurality of fins 18, can be a crystalline or non-crystalline oxide. In one embodiment, the insulator material layer 15 can be an oxide, such as for example, silicon oxide.
Preferably, the buried insulator layer 12 will be a buried oxide layer, for example, and as stated, silicon dioxide.
The SOI substrate may be formed utilizing standard processes including for example, SIMOX (separation by ion implantation of oxygen) or layer transfer. When a layer transfer process is employed, an optional thinning step may follow the bonding of two semiconductor wafers together.
As such, there is a need to improve FinFET devices and methods for making the same.